http://www.tomshardware.com/hardnews/20050620_114721.html

Check it out. Due this year.

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Oh my, sounds very promissing - especially if they are usable on desktop boards with pcie slots :)

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The way I read it that is exactly how it is designed. So who feels like porting Seti for this thing? here's the link

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Still looking for something profound or inspirational to place here.

Wow, I see it supports FFTW! It sounds like this could definitely be used as a SETI cruncher. Too bad it's most likely going to cost over 10K, which is out of my range. Does anyone know how many FLOPS are in the average work unit? I'd like to figure out how fast it would take a single card to crunch a WU.

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Based exclusively on floating point #'s and my own system and average time, about 5 1/2 minutes. I'm guessing that 45 min may be more inline. We'll see what pricing works out to ($1000-1500 and they might have some sales from people on here).

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Still looking for something profound or inspirational to place here.

If they come in anywhere under two grand, I am sooooooooo getting one of these! Even if all they're good for is BOINC. (Though I suspect some other apps will benefit, too!) And if they're a rediculous price, well, give it a few years, and then everyone will be getting them cheap.
Heh, wonder if this will cause some stagnation in the development of new processors?

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If they come in anywhere under two grand, I am sooooooooo getting one of these! Even if all they're good for is BOINC. (Though I suspect some other apps will benefit, too!) And if they're a rediculous price, well, give it a few years, and then everyone will be getting them cheap.
Heh, wonder if this will cause some stagnation in the development of new processors?

ACTUALLY if it is a hit then it may spur chip people to rethink all the money they have spent on the math chip inside the processor "for convience" and use that space for more cpu stuff. I am NOT suggesting they disable the on-board one just maybe back off a bit and let this secondary one take over and do the heavy duty processing.
We used to buy the math chip seperate "back in the day"!

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Now I'm getting confused...

They say this board needs a PCI-X slot.
I thought PCI-X is a special version of an PCI slot (100-133MHz and 64Bit)

But they also say in the FAQ
<blockquote>I am a consumer or end user, can I buy a board and plug it in my home PC?
Our boards are designed to be used as add-in cards with a standard PC.</blockquote>

Andy

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Want to know your pending credit?


The biggest bug is sitting 10 inch in front of the screen.

Now I'm getting confused...

They say this board needs a PCI-X slot.
I thought PCI-X is a special version of an PCI slot (100-133MHz and 64Bit)

But they also say in the FAQ
<blockquote>I am a consumer or end user, can I buy a board and plug it in my home PC?
Our boards are designed to be used as add-in cards with a standard PC.</blockquote>

Andy

Correct, PCI-X is NOT PCI-Express

PCI-X is a version of PCI that came before PCI-express, that is 64-bit, and normally used on only high end desktop boards and server boards.

They also say in another press release that they are considering a PCI-Express version but that current plans are for the PCI-X version first. Those of us that can afford the 2000 dollar pricetag for a MATH CO PROCESSOR, usually have the money to throw around on a high end motherboard first (and those motherboards have yet to completely adopt PCI-Express.) That's why this is the first standard it is being released for.

PCI-X 2.0 was a new, higher speed version of the conventional PCI standard, which supported signaling speeds up to 533 megatransfers per second (MTS). Revision 1.0 of the PCI-X specification defined PCI-X 66 and PCI-X 133 devices that transferred data up to 133 MTS, or over 1Gbyte per second for a 64-bit device. The present revision adds two new speed grades: PCI-X 266 and PCI-X 533, offering up to 4.3 gigabytes per second of bandwidth, 32 times faster than the first generation of PCI. Another major feature of the PCI-X 2.0 specification is enhanced system reliability. ECC support has been added both for the header and payload, providing automatic single-bit error recovery and double-bit error detection. These new standards keep pace with upcoming advances in high-bandwidth business-critical applications such as Fibre Channel, RAID, networking, InfiniBandâ„¢ Architecture, SCSI, and iSCSI.

PCI-X 2.0 is built upon the same architecture, protocols, signals, and connector as traditional PCI. The reuse of many of the design elements from the conventional PCI and PCI-X1.0b standards eases design and implementation migration. Migration to PCI-X 266 and PCI-X 533 is further simplified by retaining hardware and software compatibility with previous generations of PCI and PCI-X. As a result, new designs can immediately connect with hundreds of PCI and PCI-X products that are currently available. The combination of backwards compatibility and ease of migration provides investment protection for customers, developers, and manufacturers of existing PCI and PCI-X technologies as they migrate to PCI-X 266 and PCI-X 533.

PCI-X 2.0 also includes new features that will enhance applications in the future. It defines a new 16-bit interface width specifically designed for those applications that are constrained by space, such as embedded RAID controllers, or portable applications. PCI-X 2.0 also expands the device configuration space for each device-function to 4Kbytes, and defines a new Device ID Message transaction to enable simplified peer-to-peer transactions for applications such as streaming-media.

For over ten years, the PCI-SIG has been developing the world’s most popular bus technology. The PCI-X 2.0 266 MHz and 533 MHz standards lay the groundwork for the next decade, and further backwards-compatible extensions are planned beyond 533 MHz.

The other contender, Formerly known as 3GIO, "PCI Express" is the open standards- based successor to PCI and its variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on 32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that found in Gigabit1 Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses.

PCI Express has the following advantages over PCI:

1. Serial technology providing scalable performance.
2. High bandwidth—Initially, 5-80 gigabits per second (Gbps) peak theoretical bandwidth, depending on the implementation.
3. Point-to-point link dedicated to each device, instead of the PCI shared bus.
4. Opportunities for lower latency (or delay) in server architectures, because PCI Express provides a more direct connection to the chip set Northbridge (see Note 2) than PCI-X.
5. Small connectors and, in many cases, easier implementation for system designers.
6. Advanced features—Quality of service (QoS) via isochronous channels for guaranteed bandwidth delivery when required, advanced power management, and native hot plug/hot swap support.

PCI Express will replace the PCI, PCI-X, and AGP parallel buses gradually over the next decade, as we may already be aware of. It will initially replace buses that need the additional performance or features. For instance, PCI Express will initially be deployed as a replacement for the AGP8X graphics bus in client systems, providing high bandwidth and support for multimedia traffic. It will also COEXIST WITH and ultimately replace the PCI-X bus in server systems.

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