Currently being fabricated on a 65nm and 45nm process, ive heard of Nehalem, Westmere and Sandy Bridge on a 32nm process, and the shrink of Sandy Bridge at 22nm, plus plans for a 16nm chip, how farther can this go?

Hope you get what I mean.

---

- Luke.

That's about as far as it can go, see this article for a little more info.

-Dave

---

Currently being fabricated on a 65nm and 45nm process, ive heard of Nehalem, Westmere and Sandy Bridge on a 32nm process, and the shrink of Sandy Bridge at 22nm, plus plans for a 16nm chip, how farther can this go?

Hope you get what I mean.

Away back in 1971, I was interviewing for a Hertz Fellowship. I was an electrical engineer with a lot of semiconductor background, most recently with a co-op assignment in an IC group at Murray Hill.

My interviewer was physicist, and complained that he did not know what to ask someone of my background. So he fell back on an always safe question, and asked me what the fundamental limits to ICs were. I said I did not know, and asserted that it was not in fact known. He was not terribly happy, but can't have been too unhappy overall as I did get the fellowship.

Since then, the consistent pattern of IC fundamental limits discussions has been that the current crop of "fundamental" limits are more a guide to what has to be worked on and to change in the next few generations than to where things will stop.

Just to pick one--at one time we thought we knew about how thin silicon dioxide could go based on inherent variability of film thickness, and the need for it not to drop to zero anywhere. That forecast was wrong, not just by a significant amount, but by more than an order of magnitude.

Having said that, I have my own favorite candidate: share of world investment capital and of world technical graduates.

The incredible advances in IC capability we've seen have consumed an ever mounting share of these two resources--shares which cannot possibly rise above 100%.

In real life, it will slow long before those two bounds, as the return on additional resources invested finally drops below alternatives.

---

Currently being fabricated on a 65nm and 45nm process, ive heard of Nehalem, Westmere and Sandy Bridge on a 32nm process, and the shrink of Sandy Bridge at 22nm, plus plans for a 16nm chip, how farther can this go?

Hope you get what I mean.

Away back in 1971, I was interviewing for a Hertz Fellowship. I was an electrical engineer with a lot of semiconductor background, most recently with a co-op assignment in an IC group at Murray Hill.

My interviewer was physicist, and complained that he did not know what to ask someone of my background. So he fell back on an always safe question, and asked me what the fundamental limits to ICs were. I said I did not know, and asserted that it was not in fact known. He was not terribly happy, but can't have been too unhappy overall as I did get the fellowship.

Since then, the consistent pattern of IC fundamental limits discussions has been that the current crop of "fundamental" limits are more a guide to what has to be worked on and to change in the next few generations than to where things will stop.

Just to pick one--at one time we thought we knew about how thin silicon dioxide could go based on inherent variability of film thickness, and the need for it not to drop to zero anywhere. That forecast was wrong, not just by a significant amount, but by more than an order of magnitude.

Having said that, I have my own favorite candidate: share of world investment capital and of world technical graduates.

The incredible advances in IC capability we've seen have consumed an ever mounting share of these two resources--shares which cannot possibly rise above 100%.

In real life, it will slow long before those two bounds, as the return on additional resources invested finally drops below alternatives.

Yeah , What He Said!!

I'm sure the engineers have thought about this but everybody knows there's a third dimension. I don't know if all the transistors are in only one layer or not, but it sure looks that way. A billion (10^9) transistors per square centimeter means one transistor per every square of 316 nanometers on a side, or 10 transistors in each square micron. (One square centimeter contains 100,000,000 square microns). I don't know how thick those transistors are but I can guess it would be less than a micron. If they layer things up and each layer consisted of transistors and a dielectric separator which totaled a micron in thickness, they could stack 10,000 layers in a centimeter of thickness. One cubic centimeter would contain 10^9 * 10^4 transistors or 10^13 transistors. But right now that would melt and smoke in a flash.

---

I'm sure the engineers have thought about this but everybody knows there's a third dimension. I don't know if all the transistors are in only one layer or not, but it sure looks that way. A billion (10^9) transistors per square centimeter means one transistor per every square of 316 nanometers on a side, or 10 transistors in each square micron. (One square centimeter contains 100,000,000 square microns). I don't know how thick those transistors are but I can guess it would be less than a micron. If they layer things up and each layer consisted of transistors and a dielectric separator which totaled a micron in thickness, they could stack 10,000 layers in a centimeter of thickness. One cubic centimeter would contain 10^9 * 10^4 transistors or 10^13 transistors. But right now that would melt and smoke in a flash.

You're right, Popular Mechanics or Science and Intels website said soon thats the only way to pack more transistors on chips, I think I saw that Intels already working on it.

Think of it this way : How wide is an electron and how many of them do you need to get through the gates, pipes and traces per second without molecular friction setting things on fire ?

archae86 made a very good point : what is now being thought of as a fundamental limit might (will) get pushed back by new ideas.

Electrons getting too big ? Use photons ! Actually the main hurdle to photonic 'puters at the moment seems to be at the materials level. There is a need for some basic structures that allow to manipulate light in the same way we play around with electricity in our computers at the moment. These structure being mainly transistors (for logic) and capacitors (think RAM and registers here). Mind you that the states must be held steady only until the next refresh cycle but hey, seems light can be slippery. Some universities are working on this since the 90's with the most activity going on in Canada[citation needed]. That said Intel has so much R&D resources, who know what they'll come up with.

Future tech always feel like science fiction huh ? :)

---

mambo

This is a glimse into the future of chips and nanotechnology.

This is what Intel and Hewlett Packard researchers are doing in Trinity Collage Dublin at the CRANN institute.

http://www.crann.tcd.ie/index

Nanodevices;

Shown in Figure 1 is a gold nanowire, prepared by depositing double-stranded DNA on a silicon wafer substrate and by dipping this substrate in an aqueous dispersion of surface-modified gold nanoparticles. These positively charged gold nanoparticles are adsorbed at the negatively charged DNA template. The individual nanoparticles are subsequently enlarged and enjoined by electroless deposition of gold. The resulting wires are uniform, with a diameter of about 30 nm, and demonstrate good electrical conductivity.



CRANN researchers at Trinity College Dublin, are investigating the electrical properties of nanowires. Shown in Figure 2 is a Boron-doped silicon nanowire deposited on a silicon wafer. This nanowire has been contacted by overlaying four electrodes on top of the nanowire. The electrodes allow so-called 'four-probe' measurements, which permit the electrical characteristics of the nanowire to be clearly distinguished from those of the nanocontacts.

---