Are you ready for the next generation CPU?

Francois,

I saw you seem to be using my code base for your apps :o)

Now, what's interesting me is the 4 cores part - you wouldn't perchance be running an ES quad-core, would you? To my knowledge, no Core 2 CPU has HT enabled, do they?

Impressive performance numbers there, to be sure.

Regards,
Simon.
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No, not with 4 in parallel.

There have been a couple of people who have done some inline assembly for doing two operations at the same time to feed the execution units on pre-Core 2 CPU models, but so far, no X86 CPU has been able to execute as many ops in one cycle so there was no need :o)

I'm very interested in your code changes - what I'm trying to do with my site and the apps and How-Tos is to gather together as many capable people working on optimizations as possible. Your input is most welcome.

Regards,
Simon.
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It may be a single die, but four cores equals four cpus.
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Yes, these new Apple machines are nice, and very fast...but that is partially due to having FOUR processors. Take out three of those four processors and put it up against my AMD Athlon 64 FX 51 and let's see what happens when one processor is tested against one processor. Not trying to brag, start anything, or spread any 'flame' postings...just simply stating the facts. One processor -vs- one processor, fair is fair.

Very interesting stuff, although I must admit it is far beyond my level of knowledge. Hopefully Simon can make use of some of these ideas or coding schemes in some of his upcoming releases. I very much appreciate the fact that Simon's approach is to elicit input from other programmers, and work together with them for a common cause. He has already done some great work, but who knows what working with other like minded people could come up with? Thank You to Simon and all you others who are willing to share your expertise and work along with him!!
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The Genuine Kittyman..........accept no substitutes.

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It may be a single die, but four cores equals four cpus.

Thank you, even people with an Intel or an AMD Dual Core or Core 2 need to realize this fact...you really are running multiple CPUs, they are just packaged into one piece of hardware. (I must admit, my next home unit may just have one of those Dual Core or Core 2 AMD Chips...I just have to mow a heck of a lot of yards over the summer to afford the hardware!!!)

BTW, would Francois' processor be considered a core 2 quad? I didn't think they had been released yet. Heck, you can't hardly even buy an E6600 or E6700 off the shelf yet. Or do his connections to Intel get him an engineering sample or such?
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The Genuine Kittyman..........accept no substitutes.

I think he works for Intel?

I'm surprised by some of the responses I've seen to this thread. People are soo stuck in needing to be right or having to see things one specific way that they cannot get excited about something that is new and cool in computing. So what if it is 4 CPUs? Who cares? Are we trying to prove a point, because Francois isn't trying to prove one.

It's great for SETI and awesome for the volunteer grid computing community! WE ARE ALL IN THIS TOGETHER! Apple, AMD, Intel, IBM, etc. Whatever it takes!

[...]
If you look at the FFT using 4 vectors in parallel, you have to try to code your FFT in a way you minimize the penalities: Branching, Memory footprint, and in the case of Core, you want to use as many SSEx 128Bits instruction as you can.
to use SIMD efficenly, you want to move your data from Array of Structure to Structure of Structure.

For example, in 3D, it is very common to store X,Y,Z,W in memory like this:
X,Y,Z,W,X,Y,Z,W,X,Y,Z,W,X,Y,Z,W,X,Y,Z,W... (Array of Structure)

The natural way to store your SIMD data is
XXXXXXXXXXX....
YYYYYYYYYYYY...
ZZZZZZZZ.....
WWWWWWWWWWW... (Structure of Array)

But this have the bad side effect to open more memory streams and most of the modern processors allow only 4 or 8 streams open in the some time.
One of my co-worker, AlexK came up with this data structure in 1998 call Structure of Structure:

XXXX,YYYY,ZZZZ,WWWW,XXXX,YYYY,ZZZZ,WWWW,XXXX,YYYY,ZZZZ,WWWW...

Like this, you access only with one or 2 memory streams, your data locality is tight, and your cache lines get really efficent.
[...]
Anybody who wants to help on the SIMDized of SETI is welcome :)

FrancoisP

And the manner in which he is doing it is beyond reproach...being openly willing to share optimized code.

Noun: reproach
1. A mild rebuke or criticism; "Words of reproach"
2. Disgrace or shame; "He brought reproach upon his family"

Verb: reproach
1. Express criticism towards; "The President reproached the General for his irresponsible behavior"

And the manner in which he is doing it is beyond reproach...being openly willing to share optimized code.

I don't mean to be the resident nitpicker, but as I was reading this, I started to get the wrong impression. "Beyond reproach" is a bad thing, as defined by a dictionary:

Noun: reproach
1. A mild rebuke or criticism; "Words of reproach"
2. Disgrace or shame; "He brought reproach upon his family"

Verb: reproach
1. Express criticism towards; "The President reproached the General for his irresponsible behavior"

That isn't what you meant, is it?

The word "beyond" modify's the meaning. Now he cannot be reproached. Now it's a compliment.

Please, let's not digress ;o)

Constructive intellectual exchange is never a bad thing, though grasp of language or lack thereof kind of wasn't the original topic.

Anyway, I'd be interested to know whether I'm correct in the assumption that fundamentally, quad-core Core2 chips are feature-identical to current dual-core models.

I'm not sure whether this is information that is still under NDA or not, so of course understand if you cannot answer Francois ;o)

Regards,
Simon.
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If you look at the FFT using 4 vectors in parallel, you have to try to code your FFT in a way you minimize the penalities: Branching, Memory footprint, and in the case of Core, you want to use as many SSEx 128Bits instruction as you can.

<snip>

One of my co-worker, AlexK came up with this data structure in 1998 call Structure of Structure:

XXXX,YYYY,ZZZZ,WWWW,XXXX,YYYY,ZZZZ,WWWW,XXXX,YYYY,ZZZZ,WWWW...

Like this, you access only with one or 2 memory streams, your data locality is tight, and your cache lines get really efficent.

What I am doing today in SETI code is simply trying to apply Alex idea to FFT.
I ll need few more weeks to get it done, it is a nice mind game, but it should increase dramatically the intruction per clock on the FFT side.

And the manner in which he is doing it is beyond reproach...being openly willing to share optimized code.

I don't mean to be the resident nitpicker, but as I was reading this, I started to get the wrong impression. "Beyond reproach" is a bad thing, as defined by a dictionary:

Noun: reproach
1. A mild rebuke or criticism; "Words of reproach"
2. Disgrace or shame; "He brought reproach upon his family"

Verb: reproach
1. Express criticism towards; "The President reproached the General for his irresponsible behavior"

That isn't what you meant, is it?

http://setiathome.berkeley.edu/show_host_detail.php?hostid=2302665

It may be a single die, but four cores equals four cpus.

ok :) if you want to count like this, it is ok.

Francois

http://setiathome.berkeley.edu/show_host_detail.php?hostid=2302665

It may be a single die, but four cores equals four cpus.

ok :) if you want to count like this, it is ok.

Francois

Back in the day, a single CPU was hundreds of vacuum tubes or a few thousand transistors.

Then we got integrated circuits, and a single (more capable) CPU was thousands of chips spread across dozens of circuit boards....

... then we could squeeze all of that onto one board.

Then the 4004 came out, and we had all of that on one chip.

http://setiathome.berkeley.edu/show_host_detail.php?hostid=2302665

It may be a single die, but four cores equals four cpus.

ok :) if you want to count like this, it is ok.

Francois

Back in the day, a single CPU was hundreds of vacuum tubes or a few thousand transistors.

Then we got integrated circuits, and a single (more capable) CPU was thousands of chips spread across dozens of circuit boards....

... then we could squeeze all of that onto one board.

Then the 4004 came out, and we had all of that on one chip.

Somewhat later, many boards had a 386 for integer calculations and a 387 FPU for floating point.

Then the FPU was integrated, then a second FPU was integrated.

How do we count these?

EDIT....and after reading the rest of the posts on the subject, maybe my usage was OK after all. I think in the context of the whole post at least, my intended meaning came through. But I would rather this post continue with the open disussions of Alex, Simon, and Francois. Or any other posts concerning the number crunching optimization they are working on.

Somewhat later, many boards had a 386 for integer calculations and a 387 FPU for floating point.

Then the FPU was integrated, then a second FPU was integrated.

How do we count these?

It sounds like you're planning to write your own FFT implementation. Are you using some other implementation as a base, or are you starting from first principles? I'd always assumed that IPP's FFT performance was already pretty good, and keeping your data in split-complex format already eliminates most of your data shuffling, while still only using two memory streams.

Also, what effects does this have with regard to the amount of memory touched per FFT (or group of FFTs)? If you're doing four 128K complex-to-complex in-place FFTs simultaneously, you're touching 4 MB per FFT per core, which is already pushing the limits of L2 cache.