If No one else will say It, Crunch3r was saying It's a bunch of hockey pucks, buffalo chips, etc, at that speed, So much for a native quad core, Intel wins.

... and if we take the view that the only meaningful benchmark for a CPU is SETI, then it might be.

There is more to life than just SETI -- or even just BOINC.

There are certainly applications that will take advantage of the better cache/memory architecture -- and those tend to be the ones that interest me when I buy computers.

I don't buy computers just for SETI.

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If No one else will say It, Crunch3r was saying It's a bunch of hockey pucks, buffalo chips, etc, at that speed, So much for a native quad core, Intel wins.

... and if we take the view that the only meaningful benchmark for a CPU is SETI, then it might be.

There is more to life than just SETI -- or even just BOINC.

There are certainly applications that will take advantage of the better cache/memory architecture -- and those tend to be the ones that interest me when I buy computers.

I don't buy computers just for SETI.

Some were beating around the bush, I'm just a bit more direct. As I've done more than just Seti and as I've noted Barcelona is still a bit early as drivers may not have been fine tuned any yet. At least It's not Balona. ;)

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The T1 Trust, PRR T1 Class 4-4-4-4 #5550, 1 of America's First HST's

I'm not willing to say the Barcelona, et al, is a bust yet - there just hasn't been time to tell one way or the other. But AMD is far from being "totally out-classed" whether it's last year's tech or next year's:

http://setiathome.berkeley.edu/workunit.php?wuid=153455517
Intel Core 2 Duo 6600 ($230):
603412137 3459934 1 Sep 2007 4:36:23 UTC 1 Sep 2007 9:51:04 UTC Over Success Done 9,889.47 52.92 52.92

AMD Opteron 165 ($100):
603412138 2894502 1 Sep 2007 12:52:05 UTC 15 Sep 2007 12:46:18 UTC Over Success Done 8,064.16 52.92 52.92

Even accounting for an optimized app and a little OC, well you figure it out ... !->

At the risk of perpetuating the off-topic, my C2D (E6400 @ 460 x 7 = 3220MHz) is crunching CPDN on one core so the RAC to the left is from the other core. It was over 1400 on Line Feed with Chicken 2.2B. I'm still hoping to get it back over 1k when the system settles down a bit (it was up to 1030 last week but took a hit when the validators went down at the weekend).

F.

Here is a good impartial review on the Barcelona.
http://blogs.pcmag.com/miller/2007/09/where_does_amds_barcelona_real.php

That is indeed good fair comment.

So, despite certain "anti-hype", the Barcelona design does indeed look to stand up very well and look very good for future scaling up.

Which leads to the question: So where is the Intel so highly and so long hyped "Penryn"?...


The real comparison is for what CPUs are available for use "now". Not what vapourware is being Marketing hyped for "next month"...

Happy crunchin',
Martin

---

See new freedom: Mageia Linux
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Here is a good impartial review on the Barcelona.
http://blogs.pcmag.com/miller/2007/09/where_does_amds_barcelona_real.php

That is indeed good fair comment.

So, despite certain "anti-hype", the Barcelona design does indeed look to stand up very well and look very good for future scaling up.

Which leads to the question: So where is the Intel so highly and so long hyped "Penryn"?...


The real comparison is for what CPUs are available for use "now". Not what vapourware is being Marketing hyped for "next month"...

Happy crunchin',
Martin

LOL, K10 on seti stand very well? hahahaa... speaking about hype, this is a good one ... where did you see this?

Part of designing a good processor is a trade between fast clock and high instruction per clock, and high instruction per clock design force you to shorten the pipeline, making impossible to increase frequency.

You could design a core with better IPC than core 2, the problem will be to get it to clock high enough to compete with the very good trade of core 2.
For the moment, K10 at its frequency can not even compete with the old good Conroe, so, stop comparing it to Penryn, it is more than funny.

AMD did some choice into their design, it looks like they can't even have all the core working, since they are anouncing 3 cores K10 ... outch!


who?

Here is a good impartial review on the Barcelona.
http://blogs.pcmag.com/miller/2007/09/where_does_amds_barcelona_real.php

That is indeed good fair comment.

So, despite certain "anti-hype", the Barcelona design does indeed look to stand up very well and look very good for future scaling up.

Which leads to the question: So where is the Intel so highly and so long hyped "Penryn"?...


The real comparison is for what CPUs are available for use "now". Not what vapourware is being Marketing hyped for "next month"...

Happy crunchin',
Martin

I haven't seen any WU results from the posted Barcelona's here that would suggest it's a screamer, quite the contrary. It's an over hyped, late to market processor and unless they price it as such they're going to take a beating.

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Exactly what am I missing in Martins' statement? Where does he say it "looks to stand up well AT SETI"??? I think people are reading things into his statement.

My 2C

Exactly what am I missing in Martins' statement? Where does he say it "looks to stand up well AT SETI"??? I think people are reading things into his statement.

My 2C

What you are missing is the benchmarks in the link he added, a lot of claim in this article, nothing to back it up.

it is time to stop hyping something that prooved to be slow on the test ran every where.

who?

Exactly what am I missing in Martins' statement? Where does he say it "looks to stand up well AT SETI"??? I think people are reading things into his statement.

My 2C

What you are missing is the benchmarks in the link he added, a lot of claim in this article, nothing to back it up.

it is time to stop hyping something that prooved to be slow on the test ran every where.



who?

it is alive!!!

Exactly what am I missing in Martins' statement? Where does he say it "looks to stand up well AT SETI"??? I think people are reading things into his statement.

My 2C

What you are missing is the benchmarks in the link he added, a lot of claim in this article, nothing to back it up.

it is time to stop hyping something that prooved to be slow on the test ran every where.

who?

Then doesn't it follow, that you should question the link[edit]ed material[/edit], and not misinterpret his words?

... Part of designing a good processor is a trade between fast clock and high instruction per clock, and high instruction per clock design force you to shorten the pipeline, making impossible to increase frequency.

You could design a core with better IPC than core 2, the problem will be to get it to clock high enough to compete with the very good trade of core 2.
For the moment, K10 at its frequency can not even compete with the old good Conroe, so, stop comparing it to Penryn, it is more than funny. ...

And being just as funny as you Who?, perhaps I'd better not mention the Marketing-driven design fiasco of Netburst?...


Read my words again... I typed nothing of any one particular benchmark race, and that includes not specifying s@h.


Now, if you can extract your broken FPU out of your dreams, and actually come down to the real world, there is a lot lot more to a CPU and the rest of a computer system than just one Marketing skewed/screwed 'benchmark' lie.

Not to mention the unnecessary "Naughty Intel" nastyness that has very likely wasted much compute time for the unwary.

So... How does your super-design compare to such as the T1 or the T2?


I wish you a good race to keep your small present lead on s@h...

Regards,
Martin


ps: Har har har guffaw! ;-)

---

See new freedom: Mageia Linux
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AMD did some choice into their design, it looks like they can't even have all the core working, since they are anouncing 3 cores K10 ... outch!

And YOU of ALL PEOPLE should know better than for that childish swipe...

So, Intel doesn't do exactly the same for blowing a few fusable links to turn a full dud chip die into a saleable item?...

We know Intel uses exactly the same manufacturing strategy. For example, why dump on the public such cache crippled devices as such as the "Celerons". Phew!


Sorry Who?,

dirt doesn't become you.

EOF!
Martin

:-(

---

See new freedom: Mageia Linux
Take a look for yourself: Linux Format
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it is alive!!!

So... Penryn Xeons for Christmas this year.

Good stuff,

Let's see how the "tortoise and hare" race develops shall we?

Happy crunchin',
Martin

---

See new freedom: Mageia Linux
Take a look for yourself: Linux Format
The Future is what We all make IT (GPLv3)

AMD did some choice into their design, it looks like they can't even have all the core working, since they are anouncing 3 cores K10 ... outch!

And YOU of ALL PEOPLE should know better than for that childish swipe...

So, Intel doesn't do exactly the same for blowing a few fusable links to turn a full dud chip die into a saleable item?...

We know Intel uses exactly the same manufacturing strategy. For example, why dump on the public such cache crippled devices as such as the "Celerons". Phew!


Sorry Who?,

dirt doesn't become you.

EOF!
Martin

:-(

Why didn't you just call him on it directly?

The motivation behind the tri-core is marketing driven and has nothing to do with Barcelona being 'defective' in anyway as was implied.

Wired Article

Inquirer Artcile

Please note from the articles, the reason AMD can even contemplate doing this is due to the direct connect architecture which Opteron has always had and could fill a market niche Intel can't easily fill, unless they want to package three single cores into one CPU. The Wired article went on to say essentially whereas quads are making good progress in server space the uptake on desktops has been somewhat less than stellar, and this gives AMD more options as the transition towwards 4 cores and more takes place in the short term.

Also note, that even though this would give AMD an opportunity for some process salvage, I haven't read anything which says they don't have a handle on the yields with the 65nm process.

<edit>Just to be fair, the only 'salvage' CPU's I know Intel marketed were the 486SX (due to a bad FPU) and the original Celerons (due to bad integrated L2 on PIII's). IIRC, these actually turned out to be fairly popular in the low end market and Intel ended up blowing the fuse on otherwise 'good' units as well to meet demand. Also note that only the original Celeron could be considered 'junk', since you ended up with essentially no L2 at all because the MB manufacturers had eliminated MB based processor cache for PIII targeted boards. Once Intel saw there was a strong market for an entry level product, they quickly remedied that problem by developing Celeron into it's own product family.

<edit2> Reviewing the WIKI for Celeron indicates the cacheless Celeries were PII based, however I could almost swear I read at the time some were derated Mendecinos which had bad L2.

Alinator

<edit2> Reviewing the WIKI for Celeron indicates the cacheless Celeries were PII based, however I could almost swear I read at the time some were derated Mendecinos which had bad L2.

Alinator

My 400 MHz PII Deschutes has a 512K L2 Cache.
Tullio

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Why didn't you just call him on it directly?

Just demonstrating that throwing mud gets the 'sticky stuff' smeared everywhere...

The motivation behind the tri-core is marketing driven and has nothing to do with Barcelona being 'defective' in anyway as was implied.

Wired Article

Inquirer Artcile

[...]

Thanks, that is for once rather a neat and sensible Marketing niche to go for. It's even useful for the users.

It also usefully exploits AMD's architecture in a way that can't sensibly be done with the Intel design.

Should be interesting...

I wonder if AMD will go to the trouble of a die-size shrink for a dedicated and slightly more speedy triple-core varient?

Neat.


Happy crunchin',
Martin

---

See new freedom: Mageia Linux
Take a look for yourself: Linux Format
The Future is what We all make IT (GPLv3)

<edit2> Reviewing the WIKI for Celeron indicates the cacheless Celeries were PII based, however I could almost swear I read at the time some were derated Mendecinos which had bad L2.

Alinator

My 400 MHz PII Deschutes has a 512K L2 Cache.
Tullio

PII caches were on a private backside bus in the Cartridge, not integrated on the processor itself. This is what gave them the big performance advantage over all the Socket 7 machines at the time since the cache was clocked at half the CPU speed rather than at the FSB speed. The original Covington Celerons were PII's with the cache RAM left out of the cartridge.

Slot 1 PIII improved on that by integrating the L2 on the die and clocking it at full CPU speed. The 'salvage' aspect as I recall it was some early slot 1 Celerons were Mendecinos with faulty L2, derated to 266 and sold that way (equivalent to the PII based Celerons). Eventually Mendecino stood on its own as Socket 370 Celerons when Intel phased out Slot 1.

Alinator

it is alive!!!

No it isn't.

Neither Otellini nor Hinton would hint when Nehalem will see its first ship date.

Sure, this is a reason for the managers to take the design staff out to lunch to celebrate, but you have to get the parts into manufacturing and out the door before it means much of anything.

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it is alive!!!

No it isn't.

Neither Otellini nor Hinton would hint when Nehalem will see its first ship date.

Sure, this is a reason for the managers to take the design staff out to lunch to celebrate, but you have to get the parts into manufacturing and out the door before it means much of anything.

LOL...

Agreed, this doesn't mean anything more than when AMD was showing off Barcelona wafers at their developer conferences last year. ;-)

The timeframe estimates here are about as 'ironclad' as the ones the AMD gave last year too. :-)

Alinator