What (yet unsupported) instructions do we need?


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Message boards : Number crunching : What (yet unsupported) instructions do we need?

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HTH
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Message 729840 - Posted: 24 Mar 2008, 15:25:52 UTC

I asked Intel if they are going to support SSE5, SSE4a, MMX+, 3DNow! and 3DNow!+ instructions sets in Sandy Bridge. This is what I got: "...If there is a specific instruction from these extensions that you think we are missing that is useful, I would be happy to check if we have support for that functionality already..."

Can you find any instructions (from the above sets) that are yet unsupported in Intel CPUs but could be useful in SETI@home/distributed computing?
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Message 729846 - Posted: 24 Mar 2008, 15:38:31 UTC - in response to Message 729840.

I asked Intel if they are going to support SSE5, SSE4a, MMX+, 3DNow! and 3DNow!+ instructions sets in Sandy Bridge. This is what I got: "...If there is a specific instruction from these extensions that you think we are missing that is useful, I would be happy to check if we have support for that functionality already..."

Can you find any instructions (from the above sets) that are yet unsupported in Intel CPUs but could be useful in SETI@home/distributed computing?


Henri . . . might want to speak with Dr who? (Francois) regarding (seriously)


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Message 729951 - Posted: 24 Mar 2008, 19:28:59 UTC

Just out of curiosity why would Intel support AMD instruction sets and have to pay them royalties for there usage? Intel has already out performed AMD with SSE3 and SSSE3 and correct me if I’m wrong but SSE4a From AMD looks like it has some instructions for the specific true quad core design of the Barcelona and Phenom. I think that would be useless on an Intel chip. As for SSE5 AMD put it on there Barcelona core but I don’t think anyone supports it in there compilers yet. Maybe someone with a better understanding of the instruction sets will jump in and say something.
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Message 729973 - Posted: 24 Mar 2008, 20:08:14 UTC - in response to Message 729951.

Just out of curiosity why would Intel support AMD instruction sets and have to pay them royalties for there usage?


I don't know the specifics of the contract, but Intel and AMD have a cross-license deal on a lot of their technology. AMD frequently borrow's from Intel (SSEx) and Intel borrowed from AMD (x64). Royalties may be involved, I don't know. But if it's good for the customer, then it might be worth licensing (plus, how are you going to explain that your new Core 3 processor supports SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE6 but not SSE5?).
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Message 729983 - Posted: 24 Mar 2008, 20:38:28 UTC - in response to Message 729846.

Henri . . . might want to speak with Dr who? (Francois) regarding (seriously)


Yes, I will try to contact him.

Henri.
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Message 729986 - Posted: 24 Mar 2008, 20:44:24 UTC

I think we have a great deal to look forward to in Intel's AVX extensions that are planned for Sandy Bridge. It will double the register size to 256 bits meaning possibly double the throughput in a single instruction. I'm confident that there's a great deal of crunching power to be gained from that fact alone. Here's a paragraph about AVX from an Intel press briefing:


Intel AVX: The next step in the Intel instruction set -- Gelsinger also discussed Intel AVX (Advanced Vector Extensions) which, when used by software programmers, will increase performance in floating point, media, and processor intensive software. AVX can also increase energy efficiency, and is backwards compatible to existing Intel processors. Key features include wider vectors, increasing from 128 bit to 256 bit wide, resulting in up to 2x peak FLOPs output. Enhanced data rearrangement, resulting in allowing data to be pulled more efficiently, and three operand, non-destructive syntax for a range of benefits. Intel will make the detailed specification public in early April at the Intel Developer Forum in Shanghai. The instructions will be implemented in the microarchitecture codenamed "Sandy Bridge" in the 2010 timeframe.




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Message 729987 - Posted: 24 Mar 2008, 20:45:12 UTC - in response to Message 729840.

I asked Intel if they are going to support SSE5, SSE4a, MMX+, 3DNow! and 3DNow!+ instructions sets in Sandy Bridge. This is what I got: "...If there is a specific instruction from these extensions that you think we are missing that is useful, I would be happy to check if we have support for that functionality already..."

Can you find any instructions (from the above sets) that are yet unsupported in Intel CPUs but could be useful in SETI@home/distributed computing?

The answer of course is: none of them.

Some of these instructions might make things faster, but only after support is added to the appropriate compiler and/or library.

... but we're crunching now, so they aren't strictly needed.
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Message 730532 - Posted: 26 Mar 2008, 7:16:49 UTC

I haven't got an answer from Francois yet. Does anyone know where he is?

Henri.
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Message 730534 - Posted: 26 Mar 2008, 7:23:29 UTC

He more than likely busy with IDF and things.
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Message boards : Number crunching : What (yet unsupported) instructions do we need?

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