Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

---

Manned mission to Mars in 2019 Petition <-- Sign this, please.

Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

AMDSSE5 does not include SSE4, the video encoding speed is suppose to improve by 30% with AMDSSE5, while SSE4 improve by already demonstrated 60% and sometime more...

Reality is SSE4 includes intructions that are so good that they are complexe like hell, and AMD is uncapable of reproducing them.

How can you claim to be at the 5th stage of evolution, when you don't even do the 4th stage?

AMD SSE5 is all about bad marketing.

The real question should be: When a K10 with SSE4? because SSE5 is marketing smoke to hide faillure to comply.

who? Master of SSE4.

Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

AMDSSE5 does not include SSE4, the video encoding speed is suppose to improve by 30% with AMDSSE5, while SSE4 improve by already demonstrated 60% and sometime more...

Reality is SSE4 includes intructions that are so good that they are complexe like hell, and AMD is uncapable of reproducing them.

How can you claim to be at the 5th stage of evolution, when you don't even do the 4th stage?

AMD SSE5 is all about bad marketing.

The real question should be: When a K10 with SSE4? because SSE5 is marketing smoke to hide faillure to comply.

who? Master of SSE4.

... and you wonder why people criticize you? This is all marketing-speak.

If your products are so good, why do you feed the need to constantly attack them.

Worried that their processors will come in fancier packaging?

Geez.

---

Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

AMDSSE5 does not include SSE4, the video encoding speed is suppose to improve by 30% with AMDSSE5, while SSE4 improve by already demonstrated 60% and sometime more...

Reality is SSE4 includes intructions that are so good that they are complexe like hell, and AMD is uncapable of reproducing them.

How can you claim to be at the 5th stage of evolution, when you don't even do the 4th stage?

AMD SSE5 is all about bad marketing.

The real question should be: When a K10 with SSE4? because SSE5 is marketing smoke to hide faillure to comply.

who? Master of SSE4.

... and you wonder why people criticize you? This is all marketing-speak.

If your products are so good, why do you feed the need to constantly attack them.

Worried that their processors will come in fancier packaging?

Geez.

that is not marketing, it is purely Technical Mister Always Right, MPSADBW instruction improve the video encoding world dramatically, but the instruction is very complexe. So, instead of implementing it, they "invent" SSE5 without SSE4.

As one of the father of few SSEx instructions, i feel annoyed by what is done.
SSEn generation was always backward compatible with SSE(n-1), it is in the definition of SSE.

So, Mister Always Right, I am not attacking anybody, I am just saying they are not compliant with the definition of SSEn WE (Including me) designed.

Mister Always Right(M.A.R) is not qualify, because M.A.R do not work in his field, so I will pass on the fact you could have any interesting opinion on it, you are just a Fan Boy who always want to be right.

What ever you say about it, you are not a specialist on this, Go home.

who?

Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

AMDSSE5 does not include SSE4, the video encoding speed is suppose to improve by 30% with AMDSSE5, while SSE4 improve by already demonstrated 60% and sometime more...

Reality is SSE4 includes instructions that are so good that they are complex like hell, and AMD is incapable of reproducing them.

How can you claim to be at the 5th stage of evolution, when you don't even do the 4th stage?

AMD SSE5 is all about bad marketing.

The real question should be: When a K10 with SSE4? because SSE5 is marketing smoke to hide failure to comply.

who? Master of SSE4.

... and you wonder why people criticize you? This is all marketing-speak.

If your products are so good, why do you feed the need to constantly attack them.

Worried that their processors will come in fancier packaging?

Geez.

That is not marketing, it is purely Technical Mister Always Right, MPSADBW instruction improve the video encoding world dramatically, but the instruction is very complex. So, instead of implementing it, they "invent" SSE5 without SSE4.

As one of the father of few SSEx instructions, I feel annoyed by what is done.
SSEn generation was always backward compatible with SSE(n-1), it is in the definition of SSE.

So, Mister Always Right, I am not attacking anybody, I am just saying they are not compliant with the definition of SSEn WE (Including me) designed.

Mister Always Right(M.A.R) is not qualify, because M.A.R do not work in his field, so I will pass on the fact you could have any interesting opinion on it, you are just a Fan Boy who always want to be right.

What ever you say about it, you are not a specialist on this, Go home.

who?

Sounds more like AMD is just cutting corners with SSE4 so that AMD can say they have It and also have SSE5, Which does sound like Marketing Hype. So I agree with who? It's Marketing mainly, I mean how much would It cost AMD to really Support SSE4? Possibly not as much as they think, It might help If complete SSE4 support were included, But since that doesn't look like It's the case at hand, What can I say? And people who want True SSE4 support will buy an Intel cpu instead.

---

The T1 Trust, PRR T1 Class 4-4-4-4 #5550, 1 of America's First HST's

And people who want True SSE4 support will buy an Intel cpu instead.

I want 'em all.

---

Manned mission to Mars in 2019 Petition <-- Sign this, please.

I don't think it's very ingenius to complain about marketing smoke when you work for Intel. I also think many of us realize that the 'standards' you mention were written by Intel, for the purpose of marketing smoke. Witness SSE3.

Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

AMDSSE5 does not include SSE4, the video encoding speed is suppose to improve by 30% with AMDSSE5, while SSE4 improve by already demonstrated 60% and sometime more...

Reality is SSE4 includes intructions that are so good that they are complexe like hell, and AMD is uncapable of reproducing them.

How can you claim to be at the 5th stage of evolution, when you don't even do the 4th stage?

AMD SSE5 is all about bad marketing.

The real question should be: When a K10 with SSE4? because SSE5 is marketing smoke to hide faillure to comply.

who? Master of SSE4.

... and you wonder why people criticize you? This is all marketing-speak.

If your products are so good, why do you feed the need to constantly attack them.

Worried that their processors will come in fancier packaging?

Geez.

that is not marketing, it is purely Technical Mister Always Right, MPSADBW instruction improve the video encoding world dramatically, but the instruction is very complexe. So, instead of implementing it, they "invent" SSE5 without SSE4.

As one of the father of few SSEx instructions, i feel annoyed by what is done.
SSEn generation was always backward compatible with SSE(n-1), it is in the definition of SSE.

So, Mister Always Right, I am not attacking anybody, I am just saying they are not compliant with the definition of SSEn WE (Including me) designed.

Mister Always Right(M.A.R) is not qualify, because M.A.R do not work in his field, so I will pass on the fact you could have any interesting opinion on it, you are just a Fan Boy who always want to be right.

What ever you say about it, you are not a specialist on this, Go home.

who?

You are attacking AMD -- and if your product is superior, then it will show. If your product is inferior, that will also show. The attacks are unnecessary and more likely to alienate your target audience.

You're right that I don't know why AMD chose to do SSE5 and not SSE4. Unless you were in the meetings at AMD, you don't know why either.

Your statements that "they can't" are simply assumptions.

More likely, they're doing SSE5, because their marketing weasels think they can outsmart your marketing weasels. Five is bigger than four, right? It has to be better, right?

Marketing. I'm surprised they didn't go for SSE6.

Is there any significant software product today (like Office, or Photoshop) that uses SSE4? Most publishers wait for a feature set to be deployed before they add the additional support -- even if it's just compiling with new libraries, don't they?

So, SSE4 (and SSE5) at this point are great for the "Fanboys" -- on both sides, and pretty irrelevant for anyone else. It's all posturing about the future.

... and as far as I know, there is no way for me to install "posturing" in my computer and make it go any faster.

It's just marketing.

I'm not impressed by SSE4 or SSE5 because I can't use them today.

AMD does this too, when they call their next processor family "Phenom" -- we have yet to see if it is as phenomenal as the name implies.

I don't care what AMD (or Intel) calls their next chip -- when I'm ready to buy a new machine, I look at what I want the machine to do, what I need for performance, I look at power consumption, and then I buy.

The last three computers I bought have Via C3 processors in them. Not Intel or AMD.

---

Sounds more like AMD is just cutting corners with SSE4 so that AMD can say they have It and also have SSE5, Which does sound like Marketing Hype. So I agree with who? It's Marketing mainly, I mean how much would It cost AMD to really Support SSE4? Possibly not as much as they think, It might help If complete SSE4 support were included, But since that doesn't look like It's the case at hand, What can I say? And people who want True SSE4 support will buy an Intel cpu instead.

It's worse than that. By designing SSE5, AMD is trying to create the perception that they are a generation ahead of the competition.

... and since AMD doesn't have an SSE5 part for sale, it is completely irrelevant.

I can't buy one, so it's vaporware.

At the same time, Intel's SSE4 is irrelevant until you can buy the part, and buy applications that actually use SSE4.

What good is an instruction like MPSADBW if my applications don't use MPSADBW?

I know, here on the SETI boards we're interested in number crunching, and Simon and Joe and Benher and others put in a lot of time making versions that use every possible instruction in the CPU, but SETI is an exception, not the rule.

Does MPSADBW help SETI? Don't know. Who? says it helps video encoding speed, so if you don't encode video does it matter?

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Sounds more like AMD is just cutting corners with SSE4 so that AMD can say they have It and also have SSE5, Which does sound like Marketing Hype. So I agree with who? It's Marketing mainly, I mean how much would It cost AMD to really Support SSE4? Possibly not as much as they think, It might help If complete SSE4 support were included, But since that doesn't look like It's the case at hand, What can I say? And people who want True SSE4 support will buy an Intel cpu instead.

It's worse than that. By designing SSE5, AMD is trying to create the perception that they are a generation ahead of the competition.

... and since AMD doesn't have an SSE5 part for sale, it is completely irrelevant.

I can't buy one, so it's vaporware.

At the same time, Intel's SSE4 is irrelevant until you can buy the part, and buy applications that actually use SSE4.

What good is an instruction like MPSADBW if my applications don't use MPSADBW?

I know, here on the SETI boards we're interested in number crunching, and Simon and Joe and Benher and others put in a lot of time making versions that use every possible instruction in the CPU, but SETI is an exception, not the rule.

Does MPSADBW help SETI? Don't know. Who? says it helps video encoding speed, so if you don't encode video does it matter?

Also, one other point who? failed to mention is that Penryn and even Nehalem don't implement the full SSE4 specification either.

However, I will goe as far as to say forking the SIMD instruction set tree like this will likely not be a good thing for most end users and developers, no matter what moniker you end up giving it.

Alinator

HMMMM, From the AMD site:

"Barcelona" Processor Feature: SSE4a Instruction Set Writing SIMD code poses several complications. Doing 2 to 16 operations with one instruction is a powerful feature, but unless you have enough support instructions to get your data back and forth between the registers and memory, you may not always be utilizing the full potential that SIMD offers.

The SSE2 and SSE3 instruction sets include many instructions to help with this. They include packs and unpacks, shuffles, partial register move instructions, and more. These are pretty big sets, so for SSE4a to actually provide an improvement seemed like a difficult proposition. So I looked at the instructions a bit closer, and learned about the new bit field insertion and extraction instructions.

Before I start, let me mention that both of the following instructions work only on the lower 64 bits of the registers they deal with, and the upper 64 bits are undefined. When using these instructions, keep in mind that to access the upper half of any register, you'd have to shift the bits down by 64 and then do the required processing.

EXTRQ: Extract Field from Register

This instruction basically extracts a particular set of bits from one register and moves them to the register's least significant position. For example, if you want to have only the third 16 bit value in the xmm register, xmm0 (bits [47:32]) extracted and left at bits [15:0], you would use the EXTRQ instruction, and in this way,

EXTRQ xmm0, 16, 32

The first thought that came to my mind when I saw this instruction was, "Can't I do the same thing just using a shift instruction? Okay, that wouldn't clear out the rest of the bits in this 64 bit half, but I could do a mask, and then a shift...but then I'd have to use an extra register for the mask. Well, I could do two shifts, one left and one right, but then that would be two instructions."

Anyway, you get the idea. EXTRQ can be fairly useful, but not essential. Now INSERTQ, that comes close.

INSERTQ: Inserts Field from a source Register to a destination Register

This instruction takes a set of bits from one register and places those bits at ANY offset you specify (within 64 bits of course) within the destination register. For example, if you want to take a 16 bit value from xmm0 and move it to the third 16 bit value of xmm1, you would do,

INSERTQ xmm1, xmm0, 16, 32

But if you didn't have this instruction and wanted to accomplish the same thing, what would you do?

The quickest way would be to have a mask at bits [31:16] in one register, and use that mask to zero out those bits in xmm1. Then you'd have to shift the data in xmm0 to the correct location, and then merge those bits into xmm1.

So essentially INSERTQ is doing the job of three instructions in one!

If you want to do this entire process for arbitrary bit positions (in case you want to insert or extract different bits, based on other computation), you would add one more instruction here, because now the mask will also have to be shifted in place before you do the PAND. Further, if the 'source' register has more data than just the value you want to insert, then that would involve one more PAND to zero out the rest of the unwanted bits. If you put both together, you'd need to add ONE more shift for moving the mask which will zero out the bits in the 'source' register.

This means that, in order to do what INSERTQ provides - inserting a value in a register at any location, based on value stored in a register - you could potentially need to use a grand total of six SSE instructions.

If you think about it, you'll probably find a lot of places in your code where this INSERTQ instruction could save you significant time and complexity.

There are two more instructions in the SSE4a instruction set that add some more convenience - the partial stream (non-temporal hint store) instructions for floating point values. Look for future posts covering these topics.

-Rahul C.

and you can buy this today

Bulldozer
Nehalem
SSE5

When can I buy a "Nehalem" with SSE5?!? I need it!

AMDSSE5 does not include SSE4, the video encoding speed is suppose to improve by 30% with AMDSSE5, while SSE4 improve by already demonstrated 60% and sometime more...

Reality is SSE4 includes intructions that are so good that they are complexe like hell, and AMD is uncapable of reproducing them.

How can you claim to be at the 5th stage of evolution, when you don't even do the 4th stage?

AMD SSE5 is all about bad marketing.

The real question should be: When a K10 with SSE4? because SSE5 is marketing smoke to hide faillure to comply.

who? Master of SSE4.

Yes because clearly no one at AMD can possibly understand what or how SSE4 is and works... what a rediculous and foolish statement. But hey, be happy you copied their 64 bit extensions, because your 64 bit instruction set sucked and tanked...

• SSE4A Instructions—The SSE4A instructions are EXTRQ, INSERTQ, MOVNTSD, and
MOVNTSS.
- SSE4A, indicated by ECX bit 6 of CPUID function 8000_0001h.


EXTRQ Extract Field From Register 3 SSE4A

INSERTQ Insert Field 3 SSE4A

MOVNTSD
Move Non-Temporal Scalar
Double-Precision Floating-
Point
3 SSE4A

MOVNTSS
Move Non-Temporal Scalar
Single-Precision Floating-
Point
3 SSE4A

All are 128b media

Yes because clearly no one at AMD can possibly understand what or how SSE4 is and works... what a rediculous and foolish statement. But hey, be happy you copied their 64 bit extensions, because your 64 bit instruction set sucked and tanked...

Well, I don't know if it was so much that Itanium sucks as much as the market was not interested in having to run their investment in 32 bit software so crippled as to be virtually useless, just because Intel said this is where 64 bit computing is going.

Clearly, that was a move to get away from their x86 cross licensing agreements with AMD.

Alinator

Who?, please calm down. Bad products like bad apples fall of their own weight. It certainly looks like AMD is in free fall this year, but only time will tell.

In the interim, it would be more helpful to everyone if some concrete (but simple to describe) and tangible (real-not marketing) achievements could be documented here.

It might also be interesting to understand whether an "SSE" standard organization or movement actually exists. As a neophyte, I just assumed it was a marketing phrase, which could be abused by anybody.

There is no way of ridding the boards of the fan-boys, but I do get a kick out of the Via fan-boys; that takes guts.

Hmmm, AMD'SSE4a is 128 bit, Is Intels' SSE4? Perhaps that's why the departure from a standard?

Yes because clearly no one at AMD can possibly understand what or how SSE4 is and works... what a rediculous and foolish statement. But hey, be happy you copied their 64 bit extensions, because your 64 bit instruction set sucked and tanked...

Well, I don't know if it was so much that Itanium sucks as much as the market was not interested in having to run their investment in 32 bit software so crippled as to be virtually useless, just because Intel said this is where 64 bit computing is going.

Clearly, that was a move to get away from their x86 cross licensing agreements with AMD.

Alinator

Well that's true, but I refuse to let facts cloud my responses to Who's posts, as facts are rarely allowed to cloud his posts in the first place. I've bitten my tongue on the BS he spews plenty long enough. I even went to GREAT lengths to point out in a post what I think he does that is so darned annoying, but the thread I posted that on was gone in short order.

In short, if he is going to insist on posting his crap, I will respond in kind.

There is no way of ridding the boards of the fan-boys, but I do get a kick out of the Via fan-boys; that takes guts.

Why? If you've been reading carefully, you'd have read why I bought the C3 machines.

The C3 isn't fast, and it doesn't do floating point math worth a half-a-damn.

They're running as web servers and mail servers and DNS servers where the application rarely does an integer multiply. They do lots of bitwise-and, addition and subtraction, and file I/O. Lotta stuff in RAM.

They're running code where the floating point library isn't even being linked.

The big thing is that these machines run 24/7 -- they draw power 24/7.

By going with a low power processor that is good enough for what these machines do, I save significantly on my electric bill. I also get a couple more hours of run-time on my UPSes (right about 9 hours based on yesterday's test).

That's far more important for what I do than an instruction like MPSADBW that isn't even used in these applications.

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Yes because clearly no one at AMD can possibly understand what or how SSE4 is and works... what a rediculous and foolish statement. But hey, be happy you copied their 64 bit extensions, because your 64 bit instruction set sucked and tanked...

Well, I don't know if it was so much that Itanium sucks as much as the market was not interested in having to run their investment in 32 bit software so crippled as to be virtually useless, just because Intel said this is where 64 bit computing is going.

Clearly, that was a move to get away from their x86 cross licensing agreements with AMD.

Alinator

Well that's true, but I refuse to let facts cloud my responses to Who's posts, as facts are rarely allowed to cloud his posts in the first place. I've bitten my tongue on the BS he spews plenty long enough. I even went to GREAT lengths to point out in a post what I think he does that is so darned annoying, but the thread I posted that on was gone in short order.

In short, if he is going to insist on posting his crap, I will respond in kind.

Keep in mind 3 facts:
1) Who? is an engineer, used to dealing with engineers, not us "idiots".
2) If I was to guess, English is most likely a second language for him, so the statements he makes may not be as clear as he believes.
3) He works for Intel, and obviously is very dedicated to the company. I've felt that way about employers in the past.
Keeping all that in mind, it is more fun to soak up what knowledge there is to be had than to just try and flame him every time he opens his mouth.

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Boinc Button Abuser In Training >My Shrubbers<

Yes because clearly no one at AMD can possibly understand what or how SSE4 is and works... what a rediculous and foolish statement. But hey, be happy you copied their 64 bit extensions, because your 64 bit instruction set sucked and tanked...

Well, I don't know if it was so much that Itanium sucks as much as the market was not interested in having to run their investment in 32 bit software so crippled as to be virtually useless, just because Intel said this is where 64 bit computing is going.

Clearly, that was a move to get away from their x86 cross licensing agreements with AMD.

Alinator

Well that's true, but I refuse to let facts cloud my responses to Who's posts, as facts are rarely allowed to cloud his posts in the first place. I've bitten my tongue on the BS he spews plenty long enough. I even went to GREAT lengths to point out in a post what I think he does that is so darned annoying, but the thread I posted that on was gone in short order.

In short, if he is going to insist on posting his crap, I will respond in kind.

Keep in mind 3 facts:
1) Who? is an engineer, used to dealing with engineers, not us "idiots".
2) If I was to guess, English is most likely a second language for him, so the statements he makes may not be as clear as he believes.
3) He works for Intel, and obviously is very dedicated to the company. I've felt that way about employers in the past.
Keeping all that in mind, it is more fun to soak up what knowledge there is to be had than to just try and flame him every time he opens his mouth.

At the risk of drifting off topic a little bit:

1.) Well, I find that SAH NC is one of the the most technically savvy fora I've ever had the pleasure to particiapte in. I imagine a lot of the 'idiots' here are engineers or have a strong scientific/technical background.

2.) That's a pretty lame excuse for someone posting in a primarily English speaking forum in English.

3.) Just the fact that he chose to advertise to the whole community he was an Intel marketing employee (his fancy, performance analyst title aside), means he needs to be posting 'better and cleaner' than the other guy.

In light of that, and that commercial advertising is not allowed in SAH message boards, every time he make a post like his reply to Henri's opener he pushes the gray area in this regard, IMHO.

So in closing here, I take his comment:

"When a K10 with SSE4?"

and ask of him;

OK, when will we see a Penryn with the full SSE4 specification implemented?

Alinator